Si
Nanowires
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p-Si
Scale bar is 1µm
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- Fabrication steps: patterning of
gate electrodes on a glass substrate, fluid-directed assembly of the nanowires
across the gate electrodes, and lithography and metallization to form
source-drain contacts to the nanowires.
- The gate dielectric used in these experiments was either
a ca. 2-nm-thick shell of SiO2 surrounding the Si nanowires or a 20-nm-thick
layer of SiO2 deposited on the gate electrodes prior to NW assembly.
- The I-Vsd curves for a 20 nm diameter Si nanowire are linear indicating
that the metal electrodes make ohmic contacts.
- The dependence of the I-Vsd
curves on the gate voltage shows that the Si nanowires are p-type since the conductance
increases with increasingly negative Vg and decreases with increasingly
positive Vg.
